Logic synthesis

Results: 291



#Item
31Verified Planning by Deductive Synthesis in Intuitionistic Linear Logic Lucas Dixon and Alan Smaill and Alan Bundy School of Informatics, University of Edinburgh, UK {L.Dixon, A.Smaill, A.Bundy}@ed.ac.uk Abstract

Verified Planning by Deductive Synthesis in Intuitionistic Linear Logic Lucas Dixon and Alan Smaill and Alan Bundy School of Informatics, University of Edinburgh, UK {L.Dixon, A.Smaill, A.Bundy}@ed.ac.uk Abstract

Add to Reading List

Source URL: homepages.inf.ed.ac.uk

Language: English - Date: 2009-10-02 09:04:19
    32Verified Planning by Deductive Synthesis in Intuitionistic Linear Logic Lucas Dixon and Alan Smaill and Alan Bundy School of Informatics, University of Edinburgh, UK {L.Dixon, A.Smaill, A.Bundy}@ed.ac.uk Abstract

    Verified Planning by Deductive Synthesis in Intuitionistic Linear Logic Lucas Dixon and Alan Smaill and Alan Bundy School of Informatics, University of Edinburgh, UK {L.Dixon, A.Smaill, A.Bundy}@ed.ac.uk Abstract

    Add to Reading List

    Source URL: www-vvps09.imag.fr

    Language: English - Date: 2009-08-25 03:10:48
      33Pre-Proceedings of LOPSTR 2008 The 18th International Symposium on Logic-Based Program Synthesis and Transformation Michael Hanus (Ed.) Technical University of Valencia (Spain). July 2008

      Pre-Proceedings of LOPSTR 2008 The 18th International Symposium on Logic-Based Program Synthesis and Transformation Michael Hanus (Ed.) Technical University of Valencia (Spain). July 2008

      Add to Reading List

      Source URL: www.informatik.uni-kiel.de

      Language: English - Date: 2008-07-21 11:38:27
      34CLASE 2005 Preliminary Version Constructing Induction Rules for Deductive Synthesis Proofs Alan Bundy† 1,2 Lucas Dixon† 3 Jeremy Gow‡ 4 Jacques Fleuriot† 5

      CLASE 2005 Preliminary Version Constructing Induction Rules for Deductive Synthesis Proofs Alan Bundy† 1,2 Lucas Dixon† 3 Jeremy Gow‡ 4 Jacques Fleuriot† 5

      Add to Reading List

      Source URL: homepages.inf.ed.ac.uk

      Language: English - Date: 2005-05-19 12:03:26
      35Combinatory Logic and Program Synthesis Jakob Rehof Technical University of Dortmund Joint work w. B. D¨ udder, M. Martens (Dortmund) and P. Urzyczyn (Warsaw) and special thanks to Roger Hindley and the Torino λ-calcul

      Combinatory Logic and Program Synthesis Jakob Rehof Technical University of Dortmund Joint work w. B. D¨ udder, M. Martens (Dortmund) and P. Urzyczyn (Warsaw) and special thanks to Roger Hindley and the Torino λ-calcul

      Add to Reading List

      Source URL: www-seal.cs.tu-dortmund.de

      Language: English - Date: 2015-02-13 06:17:02
        36Toggle Equivalence Preserving Logic Synthesis Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax: (CDNL-TR

        Toggle Equivalence Preserving Logic Synthesis Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax: (CDNL-TR

        Add to Reading List

        Source URL: eigold.tripod.com

        Language: English - Date: 2006-07-02 02:02:18
          37Escaping Local Minima in Logic Synthesis ( and some other problems of logic synthesis preserving specification) Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax:

          Escaping Local Minima in Logic Synthesis ( and some other problems of logic synthesis preserving specification) Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax:

          Add to Reading List

          Source URL: eigold.tripod.com

          Language: English - Date: 2007-03-04 01:02:45
            38Escaping Local Minima in Logic Synthesis Eugene Goldberg (Cadence Berkeley Labs) Abstract. In this paper, we continue studying Logic Synthesis Preserving Specification (LSPS). Given a combinational circuit N and its part

            Escaping Local Minima in Logic Synthesis Eugene Goldberg (Cadence Berkeley Labs) Abstract. In this paper, we continue studying Logic Synthesis Preserving Specification (LSPS). Given a combinational circuit N and its part

            Add to Reading List

            Source URL: eigold.tripod.com

            Language: English - Date: 2007-05-20 15:46:21
              39Proposal Title: “SiGe BiCMOS Clockless Logic, Analysis, Synthesis and Systems” Lead Organization: Rensselaer Polytechnic Institute, Troy, New YorkContractor Business: OTHER EDUCATIONAL (University Education/Re

              Proposal Title: “SiGe BiCMOS Clockless Logic, Analysis, Synthesis and Systems” Lead Organization: Rensselaer Polytechnic Institute, Troy, New YorkContractor Business: OTHER EDUCATIONAL (University Education/Re

              Add to Reading List

              Source URL: www.ecse.rpi.edu

              Language: English
                40On Equivalence Checking and Logic Synthesis of Circuits with a Common Specification Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax: (

                On Equivalence Checking and Logic Synthesis of Circuits with a Common Specification Cadence Berkeley Labs 1995 University Ave.,Suite 460, Berkeley, California,94704 phone: (, fax: (

                Add to Reading List

                Source URL: eigold.tripod.com

                Language: English - Date: 2005-02-12 00:08:27